The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every substructure within any semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of a semiconductor device have resulted in very high-density circuit designs. Increasingly dense circuit design has not only improved a number of performance characteristics, it has also increased the importance of, and attention to, semiconductor device properties and behaviors.
The increased packing density of the integrated circuit generates numerous challenges to the semiconductor manufacturing process. Every device must be smaller without damaging the operating characteristics of the integrated circuit devices. High packing density, low heat generation, low power consumption, and good reliability must be maintained while satisfying a number of critical performance parameters.
Commonly, system designers specify or define a number of required operational parameters (e.g., max/min voltage, signal timing) for certain circuitry segments in a system. Semiconductor devices (i.e., integrated circuits) must comply with such required parameters in order to be used in the system. For example, a system may require that a semiconductor device operate over supply voltage range of 0V to 1.2V or, in another example, a system may require that a semiconductor device provide specified timing parameters (e.g., trise(MIN), tfall(MAX)) on a particular signal.
Unfortunately, there are a large number of variables in semiconductor device manufacturing that can affect any given performance parameter. Intra-process variations, feature matching issues, and layout considerations are among a number of concerns that impact a device manufacturer's ability to provide a specified performance parameter. One common concern, especially in low-voltage, small-geometry transistor technologies, involves the issue of leakage current and problems associated therewith.
Increasingly, small-geometry transistors have proportionally higher off state leakage currents than similar large-geometry transistor technologies. Relatively high off state transistor leakage currents, and corresponding power consumption, can have a significant negative impact in a number of low-voltage applications. Consider, for example, a mobile phone or a PDA that relies on battery power. High transistor leakage current levels can cause circuitry within such a device, even when not in use, to drain battery power very rapidly. This, of course, presents a number of problems for the user, the end-equipment manufacturer, and the semiconductor device manufacturer. A number of efforts have, therefore, been made in an attempt to control or limit transistor leakage currents—especially in the off state.
In many applications, for example, a small switch transistor is employed, in either a header switch or footer switch configuration, to shut off certain circuitry or circuit segments during periods of operational inactivity. In comparison to surrounding transistors, such switch transistors are commonly very small. For example, a CMOS switch transistor may be somewhere on the order of 1/100th the size of an associated circuit transistor. Such a reduction in size of a switch transistor proportionally reduces its current levels, especially leakage current levels. Thus, a device utilizing such a switch transistor can greatly reduce its off state leakage current—benefiting overall system power consumption.
Unfortunately, however, switch transistors can also introduce certain performance or reliability issues into a device or system design. Commonly, relatively small switch transistors have fast on/off transition times—typically much faster than larger device components in surrounding circuitry. When a switching transistor transitions too fast, it can cause signal instabilities (e.g., ringing, overshoot) in surrounding circuitry. Adding circuitry to slow down switch transition, or to compensate for resultant instabilities, can be cumbersome and costly. As previously noted, small switch transistors also have relatively small current levels. In certain applications, current limitations of a switch transistor can affect performance levels (e.g., drive current) in surrounding circuitry.
As a result, there is a need for a system that provides accurate and manageable control of signal transition times and drive current levels for a switch transistor—one that satisfies critical system performance and power-consumption requirements while providing reliable device operation in an easy, efficient and cost-effective manner.